The capital of the Brazilian state Sergipe, Aracaju, hosted the WSCAD 2016 - XVII Simpósio em Sistemas Computacionais de Alto Desempenho from 5 to 7 October. This is an annual event that presents the main applications and tendencies in computer architecture, distributed systems and HPC. Three HPC4E papers were presented during the event:
- Silveira, D.S., Moro, G.B., da Cruz, E. H. M., Navaux, P.O.A., Mello Schnorr, L., Bampi, S.: Energy Consumption Estimation in Parallel Applications: an Analysis in Real and Theoretical Models
This paper presents a detailed energy consumption analysis, considering the energy consumption related to CPU, cache memory and main memory of parallel applications on HPC systems. Furthermore, this paper also presents the correlation between energy consumption, Speedup, and execution time. Experiments are conducted with the NAS parallel benchmarks using three different measurement tools: 1) Intel PCM, 2) Perf Linux, and 3) HP CACTI. The results show a comparison between two approaches to obtain energy consumption results. One using PCM and other using Perf and CACTI. The DRAM results show an average variation between these approaches of 47% for sequential applications, and 19% for parallel applications. The system results show that the lowest energy consumption occurs only when all physical cores are used, showing that the hyper-threading system did not bring benefits in energy consumption to the system. Moreover, the cache memories results show that the cache miss rate (regardless of the level) increases with the number of threads. However, a parallel application has lower cache memory energy consumption when compared to its sequential version.
- Pavan, P.J., Lorenzoni, R.K., Bez, J.L., Padoin, E.L., Boito, F.Z., Navaux, P.O.A.: Eficiência Energética e Desempenho de E/S com Arquiteturas de Baixa Potência
This paper presents an I/O performance and energy efficiency analysis of low-power processors when compared to conventional architectures. This study aims at evaluating the viability of using such low-power architectures as servers to file systems in HPC environments. Results have shown that using the MPSoC leads to energy efficiency up to 136 times larger than what is observed with the PC. This advantage is caused by its up to 6; 7 times lower power demand. The study concluded that a PC storage server with HDD could be replaced by multiple MPSoC with SSDs to keep a similar performance while decreasing power consumption by up to 85%.
- Nasciutti, T.C., Panetta, J.: Impacto da Arquitetura de Memória de GPGPUs na Velocidade da Computaçâo de Estênceis This paper was awarded 3rd Best Paper of the Conference.
This paper presents a memory hierarchy based performance analysis for 3D stencil computation in GPGPUs (General Purpose Graphics Processing Units). The work evaluates codes that explore shared memory, read only cache, inserting the Z loop into the kernel and register reuse. Each code is benchmarked for several stencil sizes and input domain sizes to evaluate their influence on performance. A detailed study shows the L2 cache influence on the performance and points that the preferred code is the combination of read only cache reuse, inserting the Z loop into the kernel and register reuse.